This invention relates to circuitry for biasing data bus lines in preparation for sensing data values on data lines. More particularly, this invention relates to methods and apparatus for maintaining a data bus line at a reference voltage even should the external power supply vary.
FIG. 1 is a bus schematic including a pre-charging circuit of the prior art. FIG. 1 shows data bus lines DB 30 and DB 31. To node 20 on data bus line DB 30 is connected the drain of NMOS transistor 17. To node 21 on data bus line DB 31 is coupled the drain of NMOS transistor 18. The sources of transistors 17 and 18 are each coupled to V.sub.CC. FIG. 1 also shows NMOS transistors 10, 11 and 12, each of whose gate is coupled to signal DBEQ 1. The source of each of transistors 10 and 11 is coupled to V.sub.CC. The drain of transistor 10 is coupled to the source of transistor 12 at node 20, while the drain of transistor 11 is coupled to the drain of transistor 12 at node 21. Both data bus lines DB 30 and DB 31 feed directly into a data bus sense amplifier DBSA 40 and indirectly into a number of bit line sense amplifiers via paired NMOS switches such as bit line sense amplifier BLSA 50 and NMOS transistors 14 and 13. DBSA 40 is a conventional sense amplifier whose exact composition is not important herein. BLSA 50 is typically a balanced-sensing sense amplifier as is known in the art. The control inputs of transistors 13 and 14 are both coupled to Y-select line 5.
In preparation for sensing the value of the data bus lines DB 30 and DB 31, control circuitry (not shown) will attempt to pre-charge data bus lines DB 30 and DB 31 and equalize them to V.sub.CC -V.sub.T.sbsb.N. (V.sub.CC is the power supply; V.sub.T.sbsb.N is the threshold voltage of an N-channel transistor.) Accordingly, the control circuitry raises signal DBEQ 1 to HIGH. As a result, transistors 10 and 11 are turned on, and data bus lines DB 30 and DB 31 are pre-charged through transistors 10 and 11. Transistor 12 helps to insure that the charges on the two lines are equal. The final potential of data bus lines DB 30 and DB 31 is V.sub.CC -V.sub.T.sbsb.N.
Transistors 17 and 18 are weak pull-up transistors. Transistors 17 and 18 provide a weak but constant pull on data bus lines DB 30 and DB 31 to the potential V.sub.CC -V.sub.T.sbsb.N. Transistors 10, 11 and 12 are significantly more powerful than transistors 17 and 18.
When Y-select 5 turns on after BLSA 50 completes its sensing action, data bus lines DB 30 and DB 31 begin to follow bit lines Bit 35 and Bit 36, respectively. If bit line Bit 35 is "1" and bit line Bit 36 is "0," then data bus DB 30 remains at V.sub.CC -V.sub.T.sbsb.N, while BLSA 50 pulls data bus line DB 31 low through the Y-select switch 13. Without transistors 17 and 18, BLSA 50 would pull data bus line DB 31 all the way to ground level. If that occurs, pre-charging data bus line DB 31 for the next operation would take an increased amount of time and would thereby limit the operation speed of the device. To prevent this deep a drop on data bus line DB 31, a circuit designer adds transistor 18 which pulls up data bus line DB 31. Hence, data bus line DB cannot drop below a certain level predetermined by circuit design as understood in the art. Since data bus line DB 31 should provide a "0" to DBSA 40, transistor 18 cannot be strong. Otherwise, the signal difference between data bus lines DB 30 and DB 31 for sensing by DBSA 40 will be too small to insure correct operation.
Transistor 17 keeps data bus line DB 30 from dropping below V.sub.CC -V.sub.T.sbsb.N due to, say, leakage or coupling noise from neighboring signal lines (not shown).
Transistors 10, 11 and 12 are sufficiently strong to pull data bus line DB 31 to V.sub.CC -V.sub.T.sbsb.N for a short DBEQ signal.
When the source V.sub.CC is fixed, the operation of the above circuit is as expected. However, in circuits subject to power surges and power ebbs and in circuits where sudden large currents may be switched on and off, the source V.sub.CC is not fixed and can vary from a voltage V.sub.CC.sbsb.1 to a lower voltage V.sub.CC.sbsb.2. In such cases, with the pre-charger of FIG. 1, there is no circuitry to pull data bus lines DB 30 and DB 31 down to V.sub.CC.sbsb.2 -V.sub.T.sbsb.N. N channel transistors coupled to V.sub.CC can only bring data bus lines DB 30 and DB 31 up to V.sub.CC -V.sub.T.sbsb.N. In other words, N channel transistors can respond only to rising V.sub.CC. In the case of falling V.sub.CC, these transistors would be off, since the gate to source voltage (V.sub.CC.sbsb.2 -(V.sub.CC.sbsb.1-V.sub.T.sbsb.N), here) would be lower than the threshold voltage V.sub.T.sbsb.N.
FIG. 4 is a timing chart illustrating the operation of the circuit of FIG. 1 in the presence of fluctuations in V.sub.CC. In FIG. 4, V.sub.CC 400 and DBEQ 410 both begin at V.sub.CC.sbsb.1 and then fall to V.sub.CC.sbsb.2. The Y-select signal 420 goes high and DBEQ 410 falls shortly thereafter. The development of the signals 430 on the data bus lines DB 30 and DB 31 is crucial to the operation of the data bus sense amplifier DBSA 40.
When V.sub.CC is V.sub.CC.sbsb.2, one of data bus signals DB 30 and DB 31 should reach V.sub.02 in order for DBSA 40 to operate correctly. However, since V.sub.CC is down to V.sub.CC.sbsb.2, the discharge of one of the signals 430 from V.sub.CC.sbsb.1 -V.sub.T.sbsb.N to V.sub.02 takes longer than the ideal case where signals 430 are already at V.sub.CC.sbsb.2 -V.sub.T.sbsb.N. (Where V.sub.CC rises, signals 430 follow the change, and the circuit of FIG. 1 operates correctly.)
To reduce a pre-charging circuit's sensitivity to fluctuating V.sub.CC sources, the prior art employs bleeding circuits or "bleeders." FIG. 2 is a schematic of one such prior art pre-charging circuit using a bleeder. FIG. 2 includes circuit 60 of FIG. 1, including pre-charging transistors 10, 11, 12, pull-up transistors 17 and 18, signal DBEQ 1 and data bus lines DB 30 and DB 31, coupled as described above. FIG. 2 also includes DBSA 40, BLSA 50 and Y-select transistors 13 and 14, coupled to each other and to circuit 60 as described above. FIG. 2 still further includes bleeder transistors 15 and 16, respectively coupled by their drains to data bus lines DB 30 and DB 31. The source of each of NMOS transistors 15 and 16 is tied to ground. The gates of transistors 15 and 16 are coupled to signal A 2.
Before attempting to sense data bus lines DB 30 and DB 31, under the condition that V.sub.CC is lowered from V.sub.CC.sbsb.1 to V.sub.CC.sbsb.2, the bus control circuitry (again not shown) asserts signal A. Transistors 15 and 16 are turned on and bleed charge off the data bus lines DB 30 and DB 31 to ground. At the time of sensing, the potentials on data bus lines DB 30 and DB 31 are lower than V.sub.CC.sbsb.1 -V.sub.T.sbsb.N and closer to V.sub.CC.sbsb.2 -V.sub.T.sbsb.N. Thus, this bleeder circuit is an improvement over the circuit of FIG. 1 when the source V.sub.CC is not constant. The bleeder of FIG. 2 has the characteristic that current flows only when the bus control circuitry asserts signal A 2, turning on bleeder transistors 15 and 16. However, while the potential of data bus lines DB 30 and DB 31 are closer to V.sub.CC.sbsb.2 -V.sub.T.sbsb.N, the potentials typically do not reach V.sub.CC.sbsb.2 -V.sub.T.sbsb.N. Time is required for the potential on data bus lines DB 30 and DB 31 to bleed off through transistors 15 and 16 and reach V.sub.CC.sbsb.2 -V.sub.T.sbsb.N. Since this bleeder is operating regardless of V.sub.CC changes, it will bring the pre-charge level of data bus lines DB 30 and DB 31 down below V.sub.CC -V.sub.T.sbsb.N just before the activation of data bus sense amplifier DBSA 40. This is so even in the case where V.sub.CC is held constant. The bleeder 15, 16 dumps a constant amount of charge from DB 30 and DB 31 to ground, regardless of the previous V.sub.CC level. Hence the data bus line potential after equalization depends on the V.sub.CC level just before equalization. These unfixed pre-charge levels of data bus lines DB 30 and DB 31 result in potentially unacceptable sensitivity in the operation of data bus sense amplifier DBSA 40.
FIG. 5 is a timing chart illustrating the operation of the circuit of FIG. 2 in the presence of fluctuations in V.sub.CC. In FIG. 5, V.sub.CC 500 and DBEQ 510 also begin at V.sub.CC.sbsb.1 and then fall to V.sub.CC.sbsb.2. The Y-select signal 520 goes high and DBEQ 510 falls shortly thereafter. As before, when V.sub.CC is V.sub.CC.sbsb.2, one of data bus signals DB 30 and DB 31 should reach V.sub.02 in order for DBSA 40 to operate correctly. The assertion of signal A 540 causes signals 530 to fall to V.sub.CC.sbsb.2 -V.sub.T.sbsb.N. This is correct operation for a falling V.sub.CC. However, signal A 540 is always asserted, even when V.sub.CC rises and the signals 530 need to be at V.sub.CC.sbsb.1 -V.sub.T.sbsb.N.
Another type of prior art pre-charging circuit uses substantially the same circuit of FIG. 2 but modifies the operation of the circuit by changing the timing of signal A 2. This third pre-charging circuit maintains signal A 2 at HIGH. Accordingly, data bus lines DB 30 and DB 31 are adjusted whenever there is a voltage drop on V.sub.CC. The advantage here is that data bus lines DB 30 and DB 31 track the voltage V.sub.CC. However, there is significant current consumption, as transistors 15 and 16 are, in essence, always on, and the pre-charge levels of data bus lines DB 30 and DB 31 are lowered, as with the circuits mentioned above. In order to limit the current consumption and the drop in the pre-charge levels of data bus lines DB 30 and DB 31, transistors 15 and 16 have a small size. The smaller transistor size, however, increases the time required to reach the desired V.sub.CC.sbsb.2 -V.sub.T.sbsb.N when V.sub.CC changes from V.sub.CC, to V.sub.CC.sbsb.2.
Accordingly, there is a need for a pre-charging circuit which accurately tracks fluctuations in the power source with less power consumption. This and other goals of the invention will be readily apparent to one of ordinary skill in the art on the reading of the disclosure below.